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EFFICIENTLY GENERATING SELECTION MASKS FOR ROW SELECTIONS WITHIN INDEXED ADDRESS SPACES
EFFICIENTLY GENERATING SELECTION MASKS FOR ROW SELECTIONS WITHIN INDEXED ADDRESS SPACES
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机译:在地址空间内有效地生成行选择的选择掩码
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摘要
Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.
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