SCALABLE INTEGRATED CIRCUIT WITH SYNAPTIC ELECTRONICS AND CMOS INTEGRATED MEMRISTORS

摘要

A reconfigurable neural circuit includes a two dimensional array including a plurality of processing nodes, wherein each processing node includes a neuron circuit, a synapse circuit, a spike timing dependent plasticity (STDP) circuit, a weight memory for storing synaptic weights, the weight memory coupled to the synapse circuit, an interconnect fabric for interconnections to and from and between the neuron circuit, the synapse circuit, the STDP circuit, the weight memory, and between a respective node in the array and other processing nodes in the array, and a connectivity memory for storing interconnect routing controls coupled to the interconnect fabric.