首页> 外国专利> Use of grapho-epitaxial directed self-assembly applications to precisely cut logic lines

Use of grapho-epitaxial directed self-assembly applications to precisely cut logic lines

机译:使用石墨外延定向自组装应用程序精确切割逻辑线

摘要

A method for patterning topography is provided. A substrate is provided with a plurality of lines. The method includes aligning and preparing a first directed self-assembly (DSA) pattern overlying the lines, transferring the first pattern to form first line cuts, aligning and preparing a second DSA pattern overlying the lines, and transferring the second pattern to form second line cuts. The DSA patterns include trenches and holes of diameter d, and each comprise a block copolymer having HCP morphology, a characteristic dimension Lo approximately equal to the line pitch, and a minority phase of the diameter d. The trenches are wet by a majority phase of the block copolymer and guide formation of the holes. The aligning and preparation of the DSA patterns include overlapping the two sets of trenches such that areas between holes of one pattern and adjacent holes of the other pattern are shared by adjacent trenches.
机译:提供了一种用于图案化地形的方法。基板设置有多条线。该方法包括:对准并准备覆盖线的第一定向自组装(DSA)图案;转移第一图案以形成第一线切口;对准并准备覆盖线的第二DSA图案;以及转移第二图案以形成第二线。削减。 DSA图案包括直径为d的沟槽和孔,并且每个都包括具有HCP形态,特征尺寸L Sub约等于线间距和直径为d的少数相的嵌段共聚物。沟槽被嵌段共聚物的多数相润湿并引导孔的形成。 DSA图案的对准和准备包括使两组沟槽重叠,使得一个图案的孔与另一图案的相邻孔之间的区域被相邻的沟槽共享。

著录项

  • 公开/公告号US9793137B2

    专利类型

  • 公开/公告日2017-10-17

    原文格式PDF

  • 申请/专利权人 TOKYO ELECTRON LIMITED;

    申请/专利号US201615230974

  • 发明设计人 MARK H. SOMERVELL;BENJAMEN M. RATHSACK;

    申请日2016-08-08

  • 分类号H01L21/302;H01L21/3213;H01L21/308;H01L21/027;H01L21/033;G03F7;G03F7/09;

  • 国家 US

  • 入库时间 2022-08-21 13:47:11

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