首页> 外国专利> BACKGROUND CALIBRATION OF INTERLEAVE TIMING ERRORS IN TIME-INTERLEAVED ANALOG TO DIGITAL CONVERTERS

BACKGROUND CALIBRATION OF INTERLEAVE TIMING ERRORS IN TIME-INTERLEAVED ANALOG TO DIGITAL CONVERTERS

机译:时间交错模拟到数字转换器中交错时序误差的背景校准

摘要

A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), according to which N samples of the input signal are acquired in N different phases and the time-interleave error of each phase is calculated. Then the sign of each of the time-interleave error is extracted and the errors are adjusted by adjusting the timing of erroneous phases. This process is repeated until all the errors are lower than a predefined level.
机译:一种在N阶时间交织模数转换器(TIADC)中执行交织时序误差的背景校准的方法,根据该方法,在N个不同相位中获取N个输入信号样本,并计算出每个相位的时间交织误差。然后,提取每个时间交织误差的符号,并通过调整错误相位的定时来调整误差。重复此过程,直到所有错误均低于预定义的级别。

著录项

  • 公开/公告号US2017093415A1

    专利类型

  • 公开/公告日2017-03-30

    原文格式PDF

  • 申请/专利权人 MULTIPHY LTD.;

    申请/专利号US201615280930

  • 发明设计人 RUSSELL ROMANO;ANTHONY EUGENE ZORTEA;

    申请日2016-09-29

  • 分类号H03M1/10;H03M1/06;H03M1/12;

  • 国家 US

  • 入库时间 2022-08-21 13:46:45

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