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High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling
High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling
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机译:高速SAR ADC,使用比较器输出触发的二进制搜索时序方案和位相关的DAC建立
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摘要
A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.
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