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Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structures

机译:用于三维存储器结构的局部陷阱特性增强的电荷陷阱层

摘要

Threshold voltage shift due to programming of a neighboring memory element can be reduced or suppressed by forming a compositionally modulated charge storage layer in a three-dimensional memory device. The compositionally modulated charge storage layer can be formed by providing an oxygen-containing dielectric silicon compound layer outside a tunneling dielectric layer, and subsequently nitriding portions of the oxygen-containing dielectric silicon compound layer only at levels of the control gate electrodes. An alternating stack of sacrificial material layers and insulating layers can be employed to form a memory stack structure therethrough. After removal of the sacrificial material layers, a nitridation process can be performed to convert physically exposed portions of the oxygen-containing dielectric silicon compound layer into silicon nitride portions, which are vertically spaced from one another by remaining oxygen-containing dielectric silicon compound portions that have inferior charge trapping property to the silicon nitride portions.
机译:通过在三维存储器件中形成成分调制的电荷存储层,可以减少或抑制由于相邻存储元件的编程引起的阈值电压偏移。可以通过在隧穿电介质层的外部提供含氧的介电硅化合物层,然后仅在控制栅电极的水平上氮化含氧的介电硅化合物层的部分来形成成分调制的电荷存储层。牺牲材料层和绝缘层的交替堆叠可被用来形成贯穿其中的存储器堆叠结构。在去除牺牲材料层之后,可以执行氮化工艺以将含氧的介电硅化合物层的物理暴露部分转换为氮化硅部分,该氮化硅部分通过保留剩余的含氧的介电硅化合物部分而彼此垂直地间隔开。对氮化硅部分具有较差的电荷俘获性能。

著录项

  • 公开/公告号US9711530B1

    专利类型

  • 公开/公告日2017-07-18

    原文格式PDF

  • 申请/专利权人 SANDISK TECHNOLOGIES LLC;

    申请/专利号US201615158954

  • 申请日2016-05-19

  • 分类号H01L21/00;H01L27/11582;H01L29/51;H01L21/02;H01L27/11573;

  • 国家 US

  • 入库时间 2022-08-21 13:45:25

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