SYSTEM AND METHOD FOR FLUSH POWER AWARE LOW POWER MODE CONTROL IN A PORTABLE COMPUTING DEVICE

摘要

Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A cache memory of the multi-core SoC not being accessed by other components of the SoC is identified and a number of dirty cache lines present in the cache memory is determined. For a low power mode of the core, an entry latency based on the number of dirty cache lines is determined, and an exit latency is determined. An entry power cost for the low power mode is also determined based on the number of dirty cache lines A determination is made whether the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost and the entry latency of the cache memory entering the first power mode.