System and method for cache-aware low-power mode control in portable computing devices

摘要

Systems and methods for improved implementation of low power modes in multicore system-on-chip (SoC) are presented. The core of a multicore SoC entering the idle state is identified. For the low power mode of the core, the entry power cost of the core and the exit power cost of the core are calculated. The working set size of the cache associated with the core is also computed. The latency for the cache to exit the core's low-power mode is calculated using the working set size. Finally, a determination is made as to whether the low power mode for the core results in a power saving compared to the active mode for the core, based in part on the core's entry and exit power costs, and the latency in which the cache leaves the low power mode.