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Adaptive technique for adjusting signal development across bit lines for read operation robustness in memory circuits
Adaptive technique for adjusting signal development across bit lines for read operation robustness in memory circuits
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机译:用于调整位线之间信号发展的自适应技术,以提高存储电路中的读取操作的鲁棒性
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摘要
In one embodiment, a memory array has a pair of bit lines for each column of 1-bit SRAM cells and a word line for each row of cells, where, during a memory read operation, the bit value stored in each cell is detectable by sensing a voltage difference developed between the corresponding bit line pair. A first signal-development circuit is coupled to one bit line to accelerate draining that bit line of charge if a first bit value is stored in the cell, and a second signal-development circuit is coupled to the other bit line to accelerate draining that other bit line of charge if a second, different bit value is stored in the cell. Pulldown devices are provided to ensure that the signal-development circuit operate properly during the pre-charge and voltage difference development phases of the memory read operation, which is now faster due to the signal-development circuits.
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