Cellular architecture and techniques of adaptive pattern layout for SoC digital low area

摘要

A CMOS device includes a first standard cell power rail (104) that extends through the cell pattern. The first track power is connected to one of a first voltage or a second voltage lower than the first voltage. The device also includes a second tril Ho energy (118) that extends through the cell pattern.The second path of energy is connected to another of the first voltage or the second voltage. The second track of energy includes an interconnect layer m2 and a set of interconnections of layer M1 is connected to the interconnect layer M1.The device also includes a set of devices for CMOS transistors between the first and second tracks energy and fed by the first and second tracks of energy. The device includes an interconnect layer M1 (124) which extends under and orthogonal to the second path of energy. The interconnection layer M1 is coupled to the set of devices with CMOS transistors.