A subliminal bulk-driven circular amplifier for applications with low supply voltage

摘要

The bulk-driven circular amplifier includes the first bulk-driven inverter (Inv.sub.1.n.), including the first and second transistor (M.sub.1.n., M.sub.2.n.), the second primary bulk-driven inverter (Inv.sub.21.n.) including the third and fourth transistor (M.sub.3.n., M.sub.4.n.), the second secondary bulk-driven inverter (Inv.sub.22.n.) including the fifth and sixth transistor (M.sub.5.n., M.sub.6.n.) and the third inverter (Inv.sub.3. n.) including the seventh and eighth transistor (M.sub.7.n., M.sub.8.n.). The gates-source (S) of the first, third, fifth and seventh transistor (M.sub.1.n., M.sub.3.n., M.sub.5.n., M.sub.7.n.) and the gate-bulk (B) of the seventh transistor (M.sub.7.n.) lead into the clamp of the supply voltage (V.sub.DD.n.). The gates-source (S) of the second, fourth, sixth and eighth transistor (M.sub.2.n., M.sub.4.n., M.sub.6.n., M.sub.8.n.) and the gate-bulk (B) of the eighth transistor (M.sub.8.n.) are grounded. The gate (G) of the first transistor (M.sub.1.n.) leads to the first clamp of the preload (V.sub.B1.n.). The gates (G) of the second, fourth and sixth transistor (M.sub.2.n., M.sub.4.n., M.sub.6.n.) lead to the clamp of the second preload (V.sub.B2 .n.). The gate (G) of the third transistor (M.sub.3.n.) leads to the clamp of the third preload (V.sub.B3.n.). The gate (G) of the fifth transistor (M.sub.5.n.) leads to the clamp of the fourth preload (V.sub.B4.n.). The gates-bulk (B) of the first and second transistor (M.sub.1.n., M.sub.2.n.) lead to the clamp of the input voltage (V.sub.in.n.). The gates-drain (D) of the first and second transistor (M.sub.1.n., M.sub.2.n.) and the gate-bulk (B) of the third, fourth, fifth and sixth transistor (M.sub.3.n ., M.sub.4.n., M.sub.5.n., M.sub.6.n.) are interconnected. The gates drain (D) of the third and fourth transistor (M.sub.3.n., M.sub.4.n.) and the gate (G) of the seventh transistor (M.sub.7.n.) are interconnected. The gates-drain (D) of the fifth and sixth transistor (M.sub.5.n., M.sub.6.n.) and the gate (G) of the eighth transistor (M.sub.8.n.) are interconnected. The gates-drain (D) of the seventh and eighth transistor (M.sub.7.n., M.sub.8.n.) leads to the clamp of the output voltage (V.sub.out.n.).