METHOD AND DEVICE FOR TESTING INTERCONNECTIONS OF MULTIPLE CHIPS IN SYSTEM-IN-PACKAGE CHIP

摘要

A method of testing interconnections of multiple chips in a system-in-package (SiP) chip (20) for used in an SiP chip (20). The SiP chip (20) at least comprises a first bare die (201) and a second bare die (202) interconnected with the first bare die (201). Both of the first bare die (201) and the second bare die (202) comprise a joint test action group (JTAG) port (2011), and the first bare die (201) and the second bare die (202) form a serially connected JTAG structure. The method comprises: step 101, configuring a port of the first bare die (201) as an output, and a port of the second bare die (202) as an input; step 102, inputting a first measurement vector via the port of the second bare die (202), and collecting a first output vector outputted from the port of the first bare die (201); step 103, determining whether the SiP chip malfunctions according to the first output vector and a preset first comparison vector. Also disclosed is a device (40) for testing interconnections of multiple chips in an SiP chip. The present invention solves the problem in the art in which interconnections of bare dies cannot be tested, thus increasing the accuracy of testing interconnections of multiple chips in an SiP chip (20).