首页> 外国专利> SHEET FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT AND METHOD FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT

SHEET FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT AND METHOD FOR PRODUCING THREE-DIMENSIONAL INTEGRATED LAMINATED CIRCUIT

机译:制作三维整体叠层电路的表格和制作三维整体叠层电路的方法

摘要

This sheet 1 for producing a three-dimensional integrated laminated circuit, which is interposed between a plurality of semiconductor chips having through-electrodes and is used to adhere the semiconductor chips to each other and obtain a three-dimensional integrated laminated circuit, is provided with at least a curable adhesive layer 13, wherein the material that constitutes the adhesive layer 13 has a pre-curing melt viscosity at 90 °C of 1.0×100-5.0×105 Pa·s, and the cured product has an average linear expansion coefficient at 0-130 °C of 45 ppm or less. This sheet 1 for producing a three-dimensional integrated laminated circuit can be used to produce a three-dimensional integrated laminated circuit in which connection resistance between the semiconductor chips does not easily change and which is highly reliable.
机译:该用于制造三维集成电路的片1设置在具有贯通电极的多个半导体芯片之间,用于使半导体芯片彼此粘接而获得三维集成电路,该片1具有:至少可固化的粘合剂层13,其中构成粘合剂层13的材料在90℃下的固化前熔融粘度为1.0×10 0 -5.0×10 5

著录项

  • 公开/公告号WO2017175480A1

    专利类型

  • 公开/公告日2017-10-12

    原文格式PDF

  • 申请/专利权人 LINTEC CORPORATION;

    申请/专利号WO2017JP05141

  • 发明设计人 NEZU YUSUKE;SUGINO TAKASHI;

    申请日2017-02-13

  • 分类号H01L25/065;C09J7;C09J11/04;C09J11/08;C09J201;H01L21/301;H01L25/07;H01L25/18;

  • 国家 WO

  • 入库时间 2022-08-21 13:29:21

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