A successive approximation analog-to-digital converter (ADC) comprises: a sample and hold device arranged to sample and hold an input signal at the beginning of a conversion cycle; a successive approximation register for sequentially accumulating a digital output from a most significant bit to a least significant bit; A comparator that compares the output of the digital-to-analog converter with the output of the sample and hold device and provides the output to the successive approximation register; Wherein the successive approximation ADC is configured to store the stored residual signal from the residual signal storage device in an input signal stored on the sample and hold device at the beginning of each conversion cycle, /RTI After each ADC pull conversion by the SAR, the analog conversion of the digital output is as close as possible to the original input signal as long as the resolution allows. However, a residual portion of the input signal that is smaller than a value that can be represented by the least significant bits of the digital output of the SAR remains. In normal operation, a series of outputs of the SAR for the same input will appear with the same digital value output and the same residual value. By storing the residue at the end of each conversion and adding the residue to the input signal of the next conversion, the residue can accumulate over time and affect the output digital value. After a number of conversions, the accumulated residue is added up to a value greater than the value represented by the least significant bit of the register, and the digital value will be a higher value than when the conversion was performed on the input signal alone. In this way, the residual signal affects the time of the output value and can therefore be considered by processing the digital output in the time domain.;
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