DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT

摘要

The delay line circuit includes a plurality of delay units configured to receive an input signal and to modify the input signal to produce a first output signal. The delay line loop also includes a variable delay line unit, the variable delay line unit having an input end configured to receive a first output signal; An output end configured to output a second output signal; A first line between an input end and an output end, the first line comprising a first inverter, a second inverter, a first speed control unit and a third inverter in series; And a second line between the input end and the output end, the second line comprising a fourth inverter, a second speed control unit, a fifth inverter and a sixth inverter in series. The delay line circuit is also configured to selectively transmit the first output signal received via either the first line or the second line.