Register transfer level simulation device for simulating bit or bus synchronization of digital electronic circuit in e.g. silicon chip, has delay unit selectively delaying digital signal of flip-flop register around variable delay time

摘要

The device has three register transfer level design units, of which two of the design units simulate digital circuits in clock ranges, and the third unit (900) simulates the function of a synchronizer with several synchronization stages. Each stage generates a synchronizing signal that is different from synchronizing signals generated by another stage of the synchronizer. The device dynamically activates or deactivates the stages that simulate a flip-flop register. A delay unit selectively delays a digital signal of the cached register around a variable delay time. Independent claims are also included for the following: (1) a synchronization module comprising a delay unit (2) a hardware description language library comprising a synchronization module (3) a computer readable storage medium comprising an instruction to execute a register transfer level simulation (4) a synchronizer simulation method for synchronizing a digital electronic circuit.