Row address control circuit semiconductor memory device including the same and method of controlling a row address

摘要

The row address control circuit of the semiconductor memory device includes a test mode setting unit, an address counter, and a row address generating unit. The test mode setting unit provides a test mode signal for determining whether to execute the test in response to the test command. The address counter generates a first address that sequentially increases. The row address generator selects either the first address or the externally input second address as a refresh address in response to the test mode signal.