INSTRUCTIONS AND LOGIC FOR LANE-BASED STRIDED SCATTER OPERATIONS

摘要

A processor includes an execution unit to execute lane-based strided scatter instructions. The execution unit includes logic to extract a first data element from each of multiple lanes within a source vector register and to extract a second data element from each lane. The execution unit includes logic to place, in a destination vector, the first data element extracted from the second lane next to the first data element extracted from the first lane, and the second data element extracted from the second lane next to the second data element extracted from the first lane. The execution unit includes logic to store each collection of data elements placed next to each other in the destination vector in contiguous locations beginning at an address computed from a base address and a respective element of an index register specified in the instruction. Each collection of data elements represents a data structure.