Computer architecture using high-speed reconfigurable circuit and high-bandwidth memory interface

摘要

The programmable device comprises one or more programming regions each including a plurality of configurable logic blocks, each of the plurality of configurable logic blocks being connected to any other configurable logic block via a programmable interconnect fabric. Selectable connection is possible. A programmable device is configured logic configured to reconfigure the hardware of one or more configurable logic blocks in a programming area independently of any other programming area in response to instructions in the instruction stream Is further provided. [Selection] Figure 1