Computer architecture using fast reconfigurable circuits and high-bandwidth memory interfaces

摘要

The programmable device includes one or more programming regions, each of which includes a plurality of configurable logic blocks, wherein each of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block via a programmable interconnect fabric. The programmable device further includes configuration logic configured to, in response to the instruction in the instruction stream, reconfigure hardware into one or more configurable logic blocks in the programming region, independent of any of the other programming regions.