Configurable and scalable bus interconnection for multi-core, multi-threaded wireless baseband modem architecture

摘要

Various aspects of the present disclosure describe a bidirectional, dual interconnect bus configured in a ring for routing data to a processor implementing a modem function. A plurality of nodes may be combined to form a ring bus comprising at least two interconnecting rings. Multiple processors can be assigned to multiple nodes. A first one of the plurality of processors may be configured to process a first data type and a second one of the plurality of processors is configured to process a second data type obtain. The data on the ring bus may be separated into a first data type and a second data type and the separated data of the first data type is routed to the first processor on one interconnection ring And the separated data of the second data type may be routed to the second processor on another interconnecting ring.