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Floating point adder, semiconductor device and control method of floating point adder

机译:浮点加法器,半导体器件和浮点加法器的控制方法

摘要

An object of the invention is to speed up processing of adding floating-point numbers. A floating-point adder includes: a first register configured to store a first fixed-point number having a predetermined number of digits corresponding to a result of accumulation of a plurality of floating-point numbers; a first conversion unit configured to convert an input first floating-point number into a second fixed-point number having the predetermined number of digits; a second register configured to store the second fixed-point number; an adder configured to add the second fixed-point number stored in the second register and the first fixed-point number stored in the first register, and store a result of the addition in the first register as the first fixed-point number; and a second conversion unit configured to convert the first fixed-point number into a second floating-point number, and output the second floating-point number.
机译:本发明的目的是加速加浮点数的处理。浮点加法器包括:第一寄存器,被配置为存储具有与多个浮点数的累加结果相对应的预定位数的第一固定点数;以及第一转换单元,被配置为将输入的第一浮点数转换为具有预定位数的第二定点数;第二寄存器,用于存储第二定点数;加法器,用于将存储在第二寄存器中的第二定点数和存储在第一寄存器中的第一定点数相加,并将相加结果存储在第一寄存器中作为第一定点数;第二转换单元,用于将第一定点数转换为第二浮点数,并输出第二浮点数。

著录项

  • 公开/公告号JP6410637B2

    专利类型

  • 公开/公告日2018-10-24

    原文格式PDF

  • 申请/专利号JP20150035141

  • 发明设计人 田中 克典;

    申请日2015-02-25

  • 分类号G06F7/483;G06F7/499;G06F17/10;

  • 国家 JP

  • 入库时间 2022-08-21 13:11:02

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