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Integrated level translator and latch for fence architecture
Integrated level translator and latch for fence architecture
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机译:集成式电平转换器和闩锁,用于栅栏架构
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摘要
The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures in SRAM cells. The integrated level translator and latch for input signals includes a first clock (CLKS) and a second clock (CLKH). The first clock (CLKS) is used as a precharge and evaluation clock with its timing being critical for forward edge and the second clock (CLKH) is a latch clock.
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