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Confined Epitaxial Regions for Semiconductor Devices and Methods of Fabricating Semiconductor Devices Having Confined Epitaxial Regions

机译:用于半导体器件的受限外延区和制造具有受限外延区的半导体器件的方法

摘要

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.
机译:描述了用于半导体器件的受限外延区域以及具有受限外延区域的半导体器件的制造方法。例如,半导体结构包括设置在半导体衬底上方并与半导体衬底连续的多个平行半导体鳍。隔离结构设置在半导体衬底上方并且邻近多个平行半导体鳍中的每一个的下部。多个平行半导体鳍中的每一个的上部突出在隔离结构的最上表面上方。外延源极和漏极区设置在与半导体鳍片的上部中的沟道区相邻的多个平行半导体鳍片的每一个中。外延源极和漏极区域不在隔离结构上横向延伸。该半导体结构还包括一个或多个栅电极,每个栅电极设置在多个平行半导体鳍中的一个或多个的沟道区上方。

著录项

  • 公开/公告号US2018158930A1

    专利类型

  • 公开/公告日2018-06-07

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201815867210

  • 申请日2018-01-10

  • 分类号H01L29/66;H01L29/78;H01L21/8234;H01L29/08;H01L29/165;

  • 国家 US

  • 入库时间 2022-08-21 13:00:41

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