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Logical L3 processing for L2 hardware switches

机译:L2硬件交换机的逻辑L3处理

摘要

A method for learning a MAC address of an end machine that is logically connected to a logical network is described. The method receives configuration data for implementing a distributed logical router having different logical ports each of which is associated with a logical port of a logical switch. The method receives a packet through a first logical port of the logical router that has a destination IP address associated with a particular logical switch that is associated with a second logical port of the logical router. In order to learn the MAC address of the end machine, the method sends a first broadcast packet with a first source MAC address to a first set of forwarding elements that implements the particular logical switch, and sends a second broadcast packet with a second source MAC address to a second set of forwarding elements that also implements the particular logical switch.
机译:描述了一种用于学习逻辑上连接到逻辑网络的终端机的MAC地址的方法。该方法接收用于实现具有不同逻辑端口的分布式逻辑路由器的配置数据,每个逻辑端口均与逻辑交换机的逻辑端口相关联。该方法通过逻辑路由器的第一逻辑端口接收分组,该分组的目的地IP地址与与逻辑路由器的第二逻辑端口相关联的特定逻辑交换机相关联。为了了解终端机的MAC地址,该方法将具有第一源MAC地址的第一广播分组发送到实现特定逻辑交换机的第一组转发元件,并发送具有第二源MAC的第二广播分组。地址到第二组转发元素,后者也实现了特定的逻辑交换。

著录项

  • 公开/公告号US9979593B2

    专利类型

  • 公开/公告日2018-05-22

    原文格式PDF

  • 申请/专利权人 NICIRA INC.;

    申请/专利号US201514945329

  • 发明设计人 ANUPAM CHANDA;PANKAJ THAKKAR;

    申请日2015-11-18

  • 分类号H04L12/24;H04L12/721;

  • 国家 US

  • 入库时间 2022-08-21 12:57:52

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