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Semiconductor heterostructures having reduced dislocation pile-ups and related methods
Semiconductor heterostructures having reduced dislocation pile-ups and related methods
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机译:减少位错堆积的半导体异质结构及相关方法
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摘要
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
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