首页> 外国专利> Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings

Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings

机译:垂直功率晶体管,底部发射极层薄,掺杂剂注入屏蔽区和终端环的沟槽中

摘要

Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
机译:公开了诸如IGBT的垂直晶体管的各种改进。改进包括在生长衬底的顶表面区域中形成周期性的高掺杂p型发射极,然后生长各种晶体管层,接着将衬底的底表面接地,然后对底部进行湿法刻蚀。表面露出重掺杂的p +层。然后在p +层上形成金属接触。在另一种改进中,边缘终止结构利用注入到沟槽中的p型掺杂剂来形成深的p型区域,以使电场成形,并在沟槽之间形成浅的p型区域,以在截止之后迅速去除空穴。在另一改进中,使用n层和分布的n +区域的双缓冲层提高了击穿电压和饱和电压。在另一种改进中,通过改变沟槽的间距在终端结构中形成不同浓度的p区。在另一个改进中,斜切的锯齿街道增加了击穿电压。

著录项

  • 公开/公告号US9825128B2

    专利类型

  • 公开/公告日2017-11-21

    原文格式PDF

  • 申请/专利权人 MAXPOWER SEMICONDUCTOR INC.;

    申请/专利号US201615259877

  • 发明设计人 HAMZA YILMAZ;

    申请日2016-09-08

  • 分类号H01L29/49;H01L29/06;H01L21/225;H01L21/265;H01L21/304;H01L21/306;H01L21/324;H01L29/66;H01L29/739;H01L29/78;H01L29/40;H01L29/10;

  • 国家 US

  • 入库时间 2022-08-21 12:55:22

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