Simulating reference voltage response in digital simulation environments

摘要

Embodiments herein describe a digital simulation environment that changes the delay of a digital signal to represent different analog reference voltages. For example, changing the length of time the digital signal is at the logical one state versus the time the digital signal is at the logical zero state may represent an analog reference voltage that is below or above an optimal value. Put differently, the digital simulation environment can insert unequal delay shifts relative to the logical one and zero states of the digital signal to represent different analog voltages. Using these unequal delay shifts, a digital simulation system can test the simulated operation of logic representing a physical system that uses an analog reference voltage as an input to determine if the logic behaves as expected.