CLOCK DATA RECOVERY (CDR) PHASE WALK SCHEME IN A PHASE-INTERPOLATERBASED TRANSCEIVER SYSTEM

摘要

Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code (306) or a crossing PI code (308) in a clock and data recovery (CDR) circuit (206) until one or more preset criteria are satisfied. One example method generally includes determining (502) that a condition has been met; based on the determination, stepping (504), in a CDR circuit (206), at least one of a data PI code (306) or a crossing PI code (308) for each cycle of a clock (302); stopping (506) the stepping based on one or more criteria to generate a predetermined state of the data PI code (306) and the crossing PI code (308), wherein the predetermined state comprises an offset between the data PI code (306) and the crossing PI code (308); receiving (508) a data stream (218); and performing (510) clock and data recovery on the data stream (218) based on the offset between the data PI code (306) and the crossing PI code (308).