Approach for an area-efficient and scalable CMOS performance

摘要

The invention provides the guided design approach to optimize the device performance for a best area-efficient layout footprint in a single-leg MOS device that is based on any of the SOI, SOS or SON technologies. The same design methodology does further cover any types of insulating and/or organic substrates that substitute the BOX or the Sapphire. The design methodology depends on a new proprietary device architecture that is also claimed in this patent. It allows the implementations of the design equations of the methodology.