首页>
外国专利>
A MULTI-CORE LOCK-FREE RATE LIMITING APPARATUS AND METHOD
A MULTI-CORE LOCK-FREE RATE LIMITING APPARATUS AND METHOD
展开▼
机译:多核无锁速率限制装置和方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
An apparatus, such as a network element, comprises a receiver to receive a plurality of packets. A memory stores instructions and forms a first and second set of virtual queues to store the plurality of packets. A processor having one or more cores with one or more packet classifiers provides a classification of a packet in the plurality of packets. The processor in communication with the memory executes instructions to transfer the packet from the receiver to a virtual queue in the first set of virtual queues based on the classification. The processor also transfers the packet from the virtual queue to a transmitter based on a demand rate value and supply rate value associated with the virtual queue.
展开▼