A METHOD AND SYSTEM TO FETCH MULTICORE INSTRUCTION TRACES FROM A VIRTUAL PLATFORM EMULATOR TO A PERFORMANCE SIMULATION MODEL

摘要

A system and a method for simulating a multicore processor design is provided. The system comprises an input/output interface, a processor, a virtual platform emulator, and a performance simulation model comprising at least one pipeline model. The input/output interface receives code instructions comprising a plurality of instructions blocks. The processor executes a code for instructing the virtual platform emulator to emulate an execution of an instructions block of the plurality of instructions blocks to generate a stream of a plurality of block derived code instructions based on the instructions block. When a mis-prediction branch in an instruction branch of the instructions block is detected, the processor instructs the virtual platform emulator to add a plurality of dummy code instructions to the stream. When a flush pipeline event is detected the processor instructs the virtual platform emulator to add a plurality of previously executed instructions to the stream in an original execution order of the previously executed instructions, and in response to each of a plurality of sequential and independent instruction requests received from a pipeline model to sequentially and independently fetch and transfer each of the plurality of block derived code instructions and at least one of the plurality of dummy code instructions and the plurality of previously executed instructions for execution and committing in the pipeline model.