Predictions of Memory Command Punctures in Computer Processors Using PAT (PUNT AVOIDANCE TABLE)

摘要

Prediction of memory instruction punctures is disclosed in a computer processor using a punt avoidance table (PAT). In an aspect, the instruction processing circuit accesses a PAT that includes entries each containing an address of a memory instruction. Upon detecting a memory instruction in the instruction stream, the instruction processing circuit determines whether the PAT contains an entry having an address of the memory instruction. If included, the command processing circuit prevents the detected memory command from preempting the memory command pending to generate an effect before at least one pending memory command that is older than the detected memory command. In some aspects, the instruction processing circuitry may, upon execution of the pending memory instruction, determine whether a threat associated with the detected memory instruction has occurred. If so, an entry for the detected memory command is generated in the PAT.