首页> 外国专利> 3D NAND - - REDUCING WEAK-ERASE TYPE READ DISTURB IN 3D NAND NON-VOLATILE MEMORY

3D NAND - - REDUCING WEAK-ERASE TYPE READ DISTURB IN 3D NAND NON-VOLATILE MEMORY

机译:3D NAND--减少3D NAND非易失性存储器中的弱擦除型读取干扰

摘要

A read process is provided for a 3D stacked memory device that provides an optimal level of channel boosting for unselected memory strings to suppress both the normal type and weak-erase type of read disturbances. The channel includes a voltage (Vbl) of bit lines, a voltage (Vsgd_unsel) of drain-side select gates, a voltage (Vsgs_unsel) of source-side select gates, a voltage (Vcg_sel) of a selected level By controlling the voltage (Vcg_unsel) of unselected levels of the memory device. The channel may be boosted by initially allowing the drain-side and source-side select gates to be in a non-conductive state to allow capacitive coupling from increasing Vcg_unsel. The drain-side and / or source-side select gates then become conductive by raising Vsgd_unsel and / or Vsgs_unsel, which stops boosting. Additionally, boosting may occur by causing the drain-side and / or source-side selection gates to become non-conductive again while Vcg_unsel is still increasing. Alternatively, the channel may be driven at Vbl. Two-stage boosting drives the channel at Vbl, followed by boosting by capacitive coupling.
机译:为3D堆叠存储设备提供了一种读取过程,该过程为未选择的存储串提供了最佳水平的通道提升,以抑制正常类型的读取干扰和弱擦除类型的读取干扰。该沟道包括位线的电压(Vbl),漏极侧选择栅的电压(Vsgd_unsel),源极侧选择栅的电压(Vsgs_unsel),选定电平的电压(Vcg_sel)通过控制电压( Vcg_unsel)存储设备的未选定级别。可以通过首先允许漏极侧和源极侧选择栅极处于非导电状态以允许电容耦合不因Vcg_unsel增大而增强沟道。然后,通过升高Vsgd_unsel和/或Vsgs_unsel来使漏极侧和/或源极侧选择栅极导通,从而停止升压。另外,当Vcg_unsel仍在增加时,通过使漏极侧和/或源极侧选择栅极再次变为非导通状态,可以产生升压。替代地,可以以Vb1驱动通道。两级升压以Vbl驱动通道,然后通过电容耦合进行升压。

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