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3D NAND - - REDUCING WEAK-ERASE TYPE READ DISTURB IN 3D NAND NON-VOLATILE MEMORY
3D NAND - - REDUCING WEAK-ERASE TYPE READ DISTURB IN 3D NAND NON-VOLATILE MEMORY
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机译:3D NAND--减少3D NAND非易失性存储器中的弱擦除型读取干扰
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摘要
A read process is provided for a 3D stacked memory device that provides an optimal level of channel boosting for unselected memory strings to suppress both the normal type and weak-erase type of read disturbances. The channel includes a voltage (Vbl) of bit lines, a voltage (Vsgd_unsel) of drain-side select gates, a voltage (Vsgs_unsel) of source-side select gates, a voltage (Vcg_sel) of a selected level By controlling the voltage (Vcg_unsel) of unselected levels of the memory device. The channel may be boosted by initially allowing the drain-side and source-side select gates to be in a non-conductive state to allow capacitive coupling from increasing Vcg_unsel. The drain-side and / or source-side select gates then become conductive by raising Vsgd_unsel and / or Vsgs_unsel, which stops boosting. Additionally, boosting may occur by causing the drain-side and / or source-side selection gates to become non-conductive again while Vcg_unsel is still increasing. Alternatively, the channel may be driven at Vbl. Two-stage boosting drives the channel at Vbl, followed by boosting by capacitive coupling.
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