Circuits, systems and methods for providing asynchronous sample rate conversion for an oversampling sigma-delta analog-to-digital converter

摘要

A variable output data rate converter circuit preferably satisfies performance requirements while keeping the circuit complexity low. In some embodiments, the converter circuit may include an oversampling sigma-delta modulator circuit for quantizing an analog input signal at an oversampled rate and outputting a sigma-delta modulated signal, a transposed polynomial decimator circuit for decimating the sima-delta modulated signal and outputting a first decimated signal, and an integer decimator circuit for decimating the first decimated signal by an integer factor and outputting a second decimated signal at a desired output data rate. The transposed polynomial decimator circuit comprises a transposed polynomial filter circuit and a digital phase locked loop circuit which tracks a ratio between a sampling rate of the first decimated signal and the oversampled rate and outputs an intermediate sampling position parameter to the transposed polynomial filter circuit.