A new design methodology for voltage-to-frequency converters (VFCs) circuits suitable for time-based analog-to-digital converters (T-ADCs)

摘要

Analog-to-digital converter (ADC) is one of the crucial blocks for the software defined radio applications that require higher resolution, and less power consumption; accordingly, time-based analog to digital converters (T-ADC) are introduced to make use of the technology scaling, achieving low-power consumption and high-speed compared to traditional ADCs. T-ADC is composed of two parts voltage-to-time converter and time-to-digital converter; the proposed design is based on converting the voltage to frequency instead of time using the voltage-to-frequency converter. The new methodology increases the circuit sensitivity, and reduces the linearity error. Furthermore, the new methodology enhances the maximum input frequency, effective number of bits (ENOB), and signal to noise and distortion ratio (SNDR). In the proposed study, the maximum input frequency increases up to 74.8 MHz with linearity error of 3%, sensitivity of 43.24 GHz/V, ENOB of 2.79 bits and SNDR of 18.54 dB using TSMC 65 nm CMOS technology with a supply voltage of 1.2 V.