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SLIT STRESS MODULATION IN SEMICONDUCTOR SUBSTRATES

机译:半导体基底中的切应力调制

摘要

A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.
机译:公开的用于调制半导体衬底中的缝隙应力的示例包括控制将第一材料施加到半导体衬底的第一工艺。半导体衬底包括在相邻的堆叠的晶体管层之间的缝隙。第一材料涂覆狭缝的壁,以将相邻的堆叠的晶体管层之间的狭缝的第一宽度减小到第二宽度。控制第二过程以将第二材料施加到半导体衬底。第二材料将被沉积在狭缝的第二宽度中。第一材料和第二材料在相邻的堆叠的晶体管层之间的狭缝中形成固体结构。

著录项

  • 公开/公告号EP3424076A1

    专利类型

  • 公开/公告日2019-01-09

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号EP20170760440

  • 申请日2017-01-27

  • 分类号H01L21/762;H01L21/8234;H01L21/8238;H01L27/118;

  • 国家 EP

  • 入库时间 2022-08-21 12:25:47

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