Clock data recovery circuit, timing controller, electronic device, clock data recovery method

摘要

PROBLEM TO BE SOLVED: To provide a PLL-system CDR circuit capable of regenerating a clock in a short time.SOLUTION: A VCO 60 generates a plurality of clock signals CK1 to CK4 (multi-phase clock signal CKm) having a frequency fm according to control voltage Vcnt2. A phase comparator 10 compares a phase of input data Dwith a phase of each of the plurality of clock signals CK1 to CK4. A frequency comparator 20 compares a frequency fof the input data Dwith the frequency fm of the multi-phase clock signal CKm. A charge pump circuit 40 adjusts the control voltage Vcnt2 according to a phase difference signal PD and a phase frequency difference signal PFD. A dummy clock signal generator 80 generates a dummy clock signal CKd having substantially the same frequency as the frequency fm during the period during which the frequency fm is stable. In a state in which the input data Dis not input, the frequency comparator 20 compares a frequency fd of the dummy clock signal CKd with the frequency fm of the multi-phase clock signal CKm.SELECTED DRAWING: Figure 1