首页>
外国专利>
Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry
Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry
展开▼
机译:涉及锁环电路,时钟信号对准,相位平均反馈时钟电路的系统和方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.
展开▼