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Clock control system and method using circuitry operating at lower clock frequency for selecting and synchronizing the switching of higher frequency clock signals
Clock control system and method using circuitry operating at lower clock frequency for selecting and synchronizing the switching of higher frequency clock signals
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机译:时钟控制系统和方法,其使用在较低时钟频率下工作的电路来选择和同步较高频率时钟信号的切换
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摘要
First and second parallel processors operate in one of plural modes including synchronous and stand-alone modes. Each processor includes a clock for selectively providing a first high frequency clock signal to both processors. Each processor also includes electronic circuitry operating at a second frequency lower than the first frequency which generates a clock selection signal that selects one of the clocks from the first and second processors to clock both processors. The electronic circuitry, in response to mode change signals, generates clock switching control signals at the lower frequency. The lower frequency clock control signals are reclocked so that they are synchronous with the first frequency clock signals before being used to select one of the clocks.
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