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3D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation

机译:具有功能块的3D堆叠式集成电路,这些功能块配置为加速人工神经网络(ANN)计算

摘要

A three-dimensional stacked integrated circuit (3D SIC) for implementing an artificial neural network (ANN) having a non-volatile memory die including an array of non-volatile memory partitions, wherein each partition of the array of non-volatile memory partitions is configured to store first parameters of a set of neurons. The 3D SIC also has a volatile memory die including an array of volatile memory partitions, wherein each partition of the array of volatile memory partitions is configured to store second parameters of the set of neurons. The 3D SIC also has a processing logic die including an array of processing logic partitions. Each one of the partitions of the array of processing logic partitions is configured to receive input data and process the input data according to the set of neurons to generate output data.
机译:一种用于实现具有包括非易失性存储分区阵列的非易失性存储管芯的人工神经网络(ANN)的三维堆叠式集成电路(3D SIC),其中,非易失性存储分区阵列的每个分区为配置为存储一组神经元的第一参数。 3D SIC还具有包括易失性存储器分区的阵列的易失性存储器裸片,其中易失性存储器分区的阵列的每个分区被配置为存储神经元集合的第二参数。 3D SIC还具有包括处理逻辑分区阵列的处理逻辑管芯。处理逻辑分区的阵列的每个分区被配置为接收输入数据并根据神经元集合处理输入数据以生成输出数据。

著录项

  • 公开/公告号US10461076B1

    专利类型

  • 公开/公告日2019-10-29

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号US201816169919

  • 发明设计人 TONY M. BREWER;

    申请日2018-10-24

  • 分类号H01L23/12;H01L27/06;H01L25/065;H01L25/10;H01L21/768;H01L23/48;H01L23/495;H01L23/31;

  • 国家 US

  • 入库时间 2022-08-21 12:14:56

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