3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED TO ACCELERATE ARTIFICIAL NEURAL NETWORK (ANN) COMPUTATION

摘要

A three-dimensional stacked integrated circuit (3D SIC) (e.g., 100 or 800) for implementing an artificial neural network (ANN) having a memory die (e.g., 102 or 104) having an array of memory partitions (e.g., 204a to 204i). Each partition of the array of memory partitions is configured to store parameters of a set of neurons (e.g., 1004, 1006, 1014, and 1016). The 3D SIC also has a processing logic die (e.g., (106) or 802) having an array of processing logic partitions (e.g., 404a to 404i). Each partition of the array of processing logic partitions is configured to: receive input data, and process the input data according to the set of neurons to generate output data.