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Electrostatic discharge protection using vertical fin CMOS technology
Electrostatic discharge protection using vertical fin CMOS technology
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机译:使用垂直鳍式CMOS技术的静电放电保护
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摘要
Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment, forming a first set of semiconductor fins vertically extending from a substrate, and forming a second set of semiconductor fins vertically extending from the substrate, the distance between the first set of fins and the second set of fins defines a length of a junction. Embodiments also include forming a first epitaxy layer on the substrate, and forming a second epitaxy layer atop a portion of the first epitaxy layer, wherein a PN junction is formed between the first epitaxy layer and the second epitaxy layer, wherein a length of the PN junction is defined by the first set of semiconductor fins and the second semiconductor fins. Embodiments include forming a first metal contact atop the first epitaxy layer, and forming a second metal contact atop the second epitaxy layer.
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