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Binary multiplier for binary vector factorization
Binary multiplier for binary vector factorization
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机译:用于二进制矢量分解的二进制乘法器
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摘要
A processor, including: decode circuitry to decode instructions; a data cache unit including circuitry to cache data for the processor; and an approximate matrix multiplication (AMM) circuit including: a data receptor circuit to receive a weight vector w and an input vector x, both of size N, and a compression regulating parameter n; a factorizer circuit to factorize w into w≅B·s, by computing a binary factorized matrix B of size N×n, and a dictionary vector s of size n; and a binary multiplier circuit to compute w^T x≅(B·s)^T x=s^T(B^T x), the binary multiplier circuit comprising a hardware accelerator circuit to compute an array product B^T x).
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机译:一种处理器,包括:解码电路,用于解码指令;数据缓存单元,包括为处理器缓存数据的电路;近似矩阵乘法电路,包括:数据接收器电路,用于接收大小均为N的权重向量w和输入向量x以及压缩调节参数n;分解器电路,通过计算大小为N×n的二进制分解矩阵B和大小为n的字典向量s,将w分解为w≅B·s。二进制乘法器电路来计算w ^ Tx≅(B·s)^ T x = <图像alt =“自定义字符” file =“ US10210137-20190219-P00001.GIF” he =“ 3.89mm” imgContent =“ character “ imgFormat =” GIF“ wi =” 1.78mm“ /> s ^ T(B ^ Tx),该二进制乘法器电路包括一个硬件加速器电路,用于计算数组乘积 B <图像alt =“自定义字符” file =“ US10210137-20190219-P00004.GIF” he =“ 3.89mm” imgContent =“ character” imgFormat =“ GIF” wi =“ 2.12mm” /> ^ T x)。
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