Binary multiplier for binary vector factorization

摘要

A processor comprising: decoder circuits for decoding instructions; a data cache unit having circuitry for caching data for the processor; and an approximate matrix multiplication (AMM) circuit comprising: a data receiver circuit for receiving a weight vector w and an input vector x, both of size N, and a compression-controlling parameter n; a factorizer circuit for factoring w in w≅B · s, by computing a binary factorized matrix B of size Nxn, and a dictionary vector s of size n; and a binary multiplier circuit for calculating w ^ T x ≅ (B s s) T T x = s T T (B T T x), the binary multiplier circuit including a hardware accelerator circuit for calculating a matrix product (B T T x ).