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Configurable pseudo dual port architecture for use with single port SRAM
Configurable pseudo dual port architecture for use with single port SRAM
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机译:可配置的伪双端口架构,用于单端口SRAM
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摘要
A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.
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