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Closepath fast incremented sum in a three-path fused multiply-add design

机译:三径融合乘加设计中的近径快速递增和

摘要

According to one general aspect, an apparatus may include a floating-point multiply-accumulate unit configured to generate a floating point result by either adding or subtracting three floating point operands: an addend, a product carry, and a product sum. The floating-point multiply-accumulate unit may include a close path adder. The close path adder may include an unincremented mantissa addition circuit configured to compute an unincremented mantissa result based upon the three floating point operands. The close path adder may also include an incremented mantissa addition circuit configured to, at least partially in parallel with the mantissa addition circuit, produce an incremented mantissa result. The close path adder may further include a selection circuit configured to produce a close path result by selecting between the unincremented mantissa result and the incremented mantissa result.
机译:根据一个一般方面,一种装置可以包括浮点乘法累加单元,该浮点乘法累加单元被配置为通过相加或减去三个浮点操作数来生成浮点结果:加数,乘积进位和乘积和。浮点乘法累加单元可以包括闭合路径加法器。闭合路径加法器可以包括配置为基于三个浮点操作数来计算未递增的尾数结果的未递增的尾数添加电路。闭合路径加法器还可包括递增的尾数相加电路,该递增的尾数相加电路被配置为至少与尾数相加电路并行地产生递增的尾数结果。闭合路径加法器还可包括选择电路,该选择电路被配置为通过在未增加的尾数结果和增加的尾数结果之间进行选择来产生闭合路径结果。

著录项

  • 公开/公告号US10140092B2

    专利类型

  • 公开/公告日2018-11-27

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号US201715430438

  • 发明设计人 ASHRAF AHMED;

    申请日2017-02-10

  • 分类号G06F7/38;G06F7/485;G06F7/487;G06F7/483;G06F7/544;

  • 国家 US

  • 入库时间 2022-08-21 12:09:08

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