首页> 外国专利> CLOSE PATH FAST INCREMENTED SUM IN THREE-PATH FUSED MULTIPLICATION-ACCUMULATION DESIGN

CLOSE PATH FAST INCREMENTED SUM IN THREE-PATH FUSED MULTIPLICATION-ACCUMULATION DESIGN

机译:三径融合乘法-累积设计中的近径快速增加和

摘要

According to one embodiment of the present invention, an electronic device includes three floating-point operations, that is, a floating-point multiplication-accumulation unit which adds or substrates an adding number, multiply carry, and multiply sum to produce a floating-point. The floating-point multiplication-accumulation unit includes a close path adder. The close path adder includes a non-incremented mantissa adding circuit that computes a non-incremented mantissa result based on three floating-point operations. The close path adder also includes an incremented mantissa adding circuit that produces a mantissa result incremented in parallel with at least partially non-incremented mantissa adding circuit. The close path adder further includes a selection circuit that produces a close path result by selecting either of the non-incremented mantissa result or the incremented mantissa result. According to the present invention, an apparatus, a system, and a method for electrical computation of mathematical operations are able to increase the speed of the cloth path of the floating-point multiplication-accumulation unit.;COPYRIGHT KIPO 2018
机译:根据本发明的一个实施例,一种电子设备包括三个浮点运算,即,浮点乘法累加单元,该浮点乘法累加单元对相加数进行加或乘积运算,乘以进位和乘和以产生浮点。 。浮点乘法累加单元包括闭合路径加法器。闭合路径加法器包括一个不递增的尾数添加电路,该电路基于三个浮点运算来计算不递增的尾数结果。闭合路径加法器还包括递增的尾数相加电路,其产生与至少部分不递增的尾数相加电路并行地递增的尾数结果。闭合路径加法器还包括选择电路,该选择电路通过选择非递增的尾数结果或递增的尾数结果来产生闭合路径结果。根据本发明,用于数学运算的电计算的装置,系统和方法能够提高浮点乘法-累加单元的布料路径的速度。COPYRIGHTKIPO 2018

著录项

  • 公开/公告号KR20180050203A

    专利类型

  • 公开/公告日2018-05-14

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20170116116

  • 发明设计人 AHMED ASHRAFUS;

    申请日2017-09-11

  • 分类号G06F7/485;G06F7/487;

  • 国家 KR

  • 入库时间 2022-08-21 12:40:06

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