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Low Distortion Sample and Hold (S/H) Circuits and Associated Methods for Use with Analog-to-Digital Converters (ADCs)
Low Distortion Sample and Hold (S/H) Circuits and Associated Methods for Use with Analog-to-Digital Converters (ADCs)
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机译:低失真采样和保持(S / H)电路以及与模数转换器(ADC)一起使用的相关方法
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摘要
A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.
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机译:采样和保持(S / H)电路包括将采样节点耦合到第一电压的电容器和携带来自输入的信号的输入线。 S / H电路还可包括将输入线耦合到采样节点的一个或多个晶体管。所述S / H电路还可包含耦合到所述一个或一个以上晶体管的一个或一个以上源极或漏极以及耦合到第二电压的开关。 S / H电路还可以包括耦合到开关和一个或多个晶体管的一个或多个栅极的保持电路,该保持电路被配置为在采样周期期间打开输入和采样节点之间的输入线。 。
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