Low Distortion Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) and Associated Methods

摘要

An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage V_ref=N*VDD, where N1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where Vref=N*VDD, where N1, wherein the first capacitor having a capacitive value that is equal to (1−N) times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (V_IN) signal as the second input to the comparator.